The IEEE standard, "1394-1995 Standard For A High Performance Serial Bus," is an international standard for implementing an inexpensive high-speed serial bus architecture which supports both asynchronous and isochronous format data transfers. Isochronous data transfers are real-time transfers which take place such that the time intervals between significant instances have the same duration at both the transmitting and receiving applications. Each packet of data transferred isochronously is transferred in its own time period. The IEEE 1394-1995 standard bus architecture provides multiple channels for isochronous data transfer between applications. A six bit channel number is broadcast with the data to ensure reception by the appropriate application. This allows multiple applications to simultaneously transmit isochronous data across the bus structure. Asynchronous transfers are traditional data transfer operations which take place as soon as possible and transfer an amount of data from a source to a destination.
The IEEE 1394-1995 standard provides a high-speed serial bus for interconnecting digital devices thereby providing a universal I/O connection. The IEEE 1394-1995 standard defines a digital interface for the applications thereby eliminating the need for an application to convert digital data to analog data before it is transmitted across the bus. Correspondingly, a receiving application will receive digital data from the bus, not analog data, and will therefore not be required to convert analog data to digital data. The cable required by the IEEE 1394-1995 standard is very thin in size compared to other bulkier cables used to connect such devices. Devices can be added and removed from an IEEE 1394-1995 bus while the bus is active. If a device is so added or removed the bus will then automatically reconfigure itself for transmitting data between the then existing nodes. A node is considered a logical entity with a unique address on the bus structure. Each node provides an identification ROM, a standardized set of control registers and its own address space.
The IEEE 1394-1995 standard defines a protocol as illustrated in FIG. 1. This protocol includes a serial bus management block 10 coupled to a transaction layer 12, a link layer 14 and a physical layer 16. The physical layer 16 provides the electrical and mechanical connection between a device or application and the IEEE 1394-1995 cable. The physical layer 16 also provides arbitration to ensure that all devices coupled to the IEEE 1394-1995 bus have access to the bus as well as actual data transmission and reception. The link layer 14 provides data packet delivery service for both asynchronous and isochronous data packet transport. This supports both asynchronous data transport, using an acknowledgement protocol, and isochronous data transport, providing real-time guaranteed bandwidth protocol for just-in-time data delivery. The transaction layer 12 supports the commands necessary to complete asynchronous data transfers, including read, write and lock. The transaction layer 12 also provides a path for isochronous management data to be transferred to the serial bus management block 10 via read operations with isochronous control compare-swap registers. The serial bus management block 10 contains an isochronous resource manager for managing isochronous data transfers. The serial bus management block 10 also provides overall configuration control of the serial bus in the form of optimizing arbitration timing, guarantee of adequate electrical power for all devices on the bus, assignment of the cycle master, assignment of isochronous channel and bandwidth resources and basic notification of errors.
Each node on the IEEE 1394-1995 serial bus provides an identification or configuration read only memory (ROM) in either a minimal or general format. The minimal ROM format includes a single quadlet (4 bytes) of data and provides only a twenty-four (24) bit company identifier. The general ROM format provides other information in addition to the company identifier. The company identifier is used to uniquely identify vendors that manufacture or specify components that are compatible with the IEEE 1394-1995 standard.
The minimal ROM format is illustrated in FIG. 2. The first byte of data has a value equal to one to specify that this ROM is of the minimal format and includes only a single quadlet. The minimal ROM implementation consists of this single quadlet of data which includes the company identifier field. The company identifier field is a twenty-four (24) bit field which includes a value representing the company or vendor that manufactured the device.
The general configuration ROM format is illustrated in FIG. 3. Each configuration ROM includes a bus.sub.-- info.sub.-- block and a root.sub.-- directory. The root.sub.-- directory contains additional entries which provide information or may provide a pointer to another directory. The directory entry format is illustrated in FIG. 4. An eight bit key is included within each directory entry. The key includes a two bit key type field and a six bit key value field. The key type field indicates the type of directory entry. The key value field specifies the particular directory entry. There are four types of entries: immediate, offset, leaf and directory. An immediate value entry has a key type of 0 and its meaning will depend on the type of entry with which it is associated. An offset entry has a key type of 1 and specifies a CRS address as a quadlet offset from the base address of the initial register space. A leaf entry has a key type of 2. A directory entry has a key type of 3. For both leaf entries and directory entries, the value of the entry specifies the number of quadlets between the current entry point and the ROM offset address.
Within the configuration ROM of FIG. 3, the info.sub.-- length entry is an eight (8) bit entry which will have a value greater than one to specify that this ROM is of the general format. The value within the info.sub.-- length entry specifies the number of quadlets contained within the following bus.sub.-- info.sub.-- block data structure. The crc.sub.-- length entry is an eight (8) bit entry which includes a value specifying how many of the following quadlets within the configuration ROM are protected by the value within the rom.sub.-- crc.sub.-- value entry. The rom.sub.-- crc.sub.-- value entry is a sixteen (16) bit entry which includes a crc value used to verify the correctness of the data within the configuration ROM, as is well known in the art.
The bus.sub.-- info.sub.-- block entry is a block of data, having a format as illustrated in FIG. 5a, which includes information about the node and the bus structure to which it is coupled. The first quadlet of the bus.sub.-- info.sub.-- block entry contains ASCII representations of the characters "1394" to specify that the bus structure is an IEEE 1394-1995 bus structure. The isochronous resource manager capable (irmc) bit specifies whether or not the node is capable of serving as the isochronous resource manager for the bus. If the irmc bit is at a logical "1" level, then the node is capable of serving as the isochronous resource manager for the bus. Otherwise, if the irmc bit is at a logical "0" level, the node is not capable of serving as the isochronous resource manager. The cycle master capable (cmc) bit specifies whether or not the node is capable of serving as the cycle master for the bus. If the cmc bit is at a logical "1" level, then the node is capable of serving as the cycle master for the bus. Otherwise, if the cmc bit is at a logical "0" level, the node is not capable of serving as the cycle master. The isochronous (isc) bit specifies whether or not the node supports isochronous operations. If the isc bit is at a logical "1" level, then the node does support isochronous operations. Otherwise, if the isc bit is at a logical "0" level, the node does not support isochronous operations. The bus manager capable (bmc) bit specifies whether or not the node is capable of serving as the bus manager for the bus. If the bmc bit is at a logical "1" level, then the node is capable of serving as the bus manager for the bus. Otherwise, if the bmc bit is at a logical "0" level, the node is not capable of serving as the bus manager.
The cyc.sub.-- clk.sub.-- acc sub-entry within the bus.sub.-- info.sub.-- block entry is an eight bit entry which specifies the accuracy of the cycle master clock of the node in parts per million. If the cmc bit is set to a logical "1" level, signalling that the node is capable of serving as the cycle master, then the cyc.sub.-- clk.sub.-- acc entry contains a value between zero (0) and one hundred (100), representing the accuracy of the cycle master clock. Otherwise, if the cmc bit is at a logical "0" level, signalling that the node is not capable of serving as the cycle master, all of the bits within the cyc.sub.-- clk.sub.-- acc entry are set to a logical "1" level.
The max.sub.-- rec sub-entry within the bus.sub.-- info.sub.-- block entry is a four bit entry which defines the maximum payload size of an asynchronous block write transaction addressed to the node. The range of the maximum payload size is from four bytes to 2048 bytes, as specified below in Table 1.
TABLE 1 ______________________________________ Values of the max.sub.-- rec entry max.sub.-- rec Maximum size in bytes (binary encoding) (decimal values) ______________________________________ 0000 Not specified 0001 4 0010 8 0011 16 0100 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 to 1111 Reserved ______________________________________
The node.sub.-- vendor.sub.-- id sub-entry within the bus.sub.-- info.sub.-- entry is a twenty four (24) bit entry which contains a value representing the node company identifier. The value within the node.sub.-- vendor.sub.-- id sub-entry is a copy of the node company identifier value within the node.sub.-- unique.sub.-- id leaf of the configuration ROM which will be discussed below. The chip.sub.-- id.sub.-- hi sub-entry is an eight (8) bit entry. The chip.sub.-- id.sub.-- low sub-entry is a thirty two (32) bit entry. Together, the values within the chip.sub.-- id.sub.-- hi and chip.sub.-- id.sub.-- low sub-entries comprise a forty (40) bit chip identifier value. The value within the chip.sub.-- id.sub.-- hi and chip.sub.-- id.sub.-- low sub-entries is a copy of the chip identifier value within the node.sub.-- unique.sub.-- id.sub.-- leaf of the configuration ROM, which will be discussed below. Together, the values within the node.sub.-- vendor.sub.-- id, chip.sub.-- id.sub.-- hi and chip.sub.-- id.sub.-- low sub-entries form a sixty four (64) bit node unique identifier value.
The root directory within the configuration ROM contains a module.sub.-- vendor.sub.-- id entry, node.sub.-- capabilities entry and node.sub.-- unique.sub.-- id entry. The module.sub.-- vendor.sub.-- id entry is a single quadlet which contains an immediate entry in the root directory that provides the company identifier of the vendor that manufactured the module. The first byte within the quadlet specifies the key type and key value for the module.sub.-- vendor.sub.-- id entry. The remaining three bytes of the quadlet contain the value representing the company identifier for the vendor.
The node.sub.-- capabilities entry of the root directory is a single quadlet which contains an immediate entry in the root directory that describes the node capabilities. The first byte within the quadlet specifies the key type and key value for the node.sub.-- capabilities entry. The remaining three bytes within the quadlet contain flags representing the capabilities of the node and specifying such things as whether or not a split.sub.-- timeout register is implemented within the node, whether or not the node uses sixty four (64) bit addressing, whether or not the node uses a fixed addressing scheme, whether or not the state.sub.-- bits.lost bit is implemented within the node and whether or not the state.sub.-- bits.dreq bit is implemented within the node.
The node.sub.-- unique.sub.-- id entry is a single quadlet leaf entry in the root directory that describes the location of the node.sub.-- unique.sub.-- id leaf within the configuration ROM. The first byte within the quadlet specifies the key type and key value for the node.sub.-- unique.sub.-- id entry. The remaining three bytes within the quadlet contain an offset value which specifies the number of quadlets from the address of the node.sub.-- unique.sub.-- id entry to the address of the node.sub.-- unique.sub.-- id leaf within the configuration ROM.
The unit.sub.-- directories field within the configuration ROM is used to provide additional information about units within a node. The value within a unit.sub.-- directory entry points to a lower level leaf value in the configuration ROM that contains unit-specific information.
The root and unit leaves field contains root.sub.-- leaf entries and unit.sub.-- leaf entries. The unit.sub.-- leaf entries are used to store information on specific units. The root.sub.-- leaf entries are used to store bus-dependent information referenced by the entries within the root.sub.-- directory. The node.sub.-- unique.sub.-- id leaf is a root.sub.-- leaf entry. The node.sub.-- unique.sub.-- id leaf has a format as illustrated in FIG. 5b and contains a node unique identifying value. The node unique identifying value is a sixty four (64) bit number appended to a company identifying value to create a globally unique eighty eight (88) bit number. The value within the node.sub.-- vendor.sub.-- id entry is the node company identifying value from the root directory. The chip.sub.-- id.sub.-- hi value and the chip.sub.-- id.sub.-- lo value together form the chip identifying value also from the root directory.
The vendor.sub.-- dependent.sub.-- information entry within the configuration ROM contains vendor specific information about the node, units and/or bus.
The information within the configuration ROM of a device is used by other devices within the IEEE 1394-1995 serial bus network to which the device is coupled, in order to fully interact with and take advantage of the capabilities of the device. The information within the configuration ROM can also be used by the user in order to obtain information about the devices within the IEEE 1394-1995 serial bus network. However, for many typical users the raw data within the configuration ROM is meaningless.
The information in an IEEE 1394-1995 configuration ROM is stored as a block of memory organized as a tree structure. Within this tree structure, different types of tree nodes hold different types of data. Errors within this data will cause inaccuracies and inconsistencies within other devices relying on this data. For typical users, it is hard to verify the accuracy of the data within a configuration ROM of a device.